1. The instruction memory address is passed from address register to memory via address bus A[31:0]

2. The instruction is fetched from memory via data bus D[31:0]

3. The instruction is decoded, and control signals are produced. The processor now knows it’s a store instruction and is aware of the registers needed.

4. The value in address register is incremented and copied back into r15 in the register bank. The incremented value is the address of the next instruction.

5. The value stored in Rn is read on bus A.

6. The immediate or offset is fetched from data in register. It is read on bus B.

7. If there is any shift in the immediate it is calculated via barrel shifter.

8. Rn and offset are subjected to ALU which computes the value by performing the operation required.

9. The computed result is the address in which data is to be stored. It is copied back into address register and passed to the memory via address bus A[31:0].

10. The value in Rd which is to be stored is read on bus B and placed in data out register

11. The value is passed to the memory via data bus D[31:0] to be stored at the address provided previously by the address bus

12. the address of the next instruction which is stored in r15 (PC) is copied to address register.

This tour demonstrates the functionality of this tool

This diagram shows the organisation of the ARM processor. It is the 3-stage pipeline ARM organisation

These boxes provide explanation about the execution of the instruction in the ARM processor

The run button starts the instruction execution. After you press run, a stop button will appear to halt the execution

The step button goes through the instruction execution step by step

The previous button goes back to the preceding step

The invisible button removes the background diagram of the processor and displays only the parts of the processor in use. After you press invisible, a visible button will appear to display the diagram again

Press on the highlighted units to get further information about these components

Register bank has sixteen 32-bit memory locations called registers (R0 to R15). R15 is the Program Counter which stores the memory address of the next instruction to be executed.

ALU which performs the arithmetic and logic functions required by the instruction set.

Barrel shifter which can shift and rotate one operand by any number of bits.

Address register selects and holds memory addresses.

Incrementer used to generate sequential addresses when required.

Data out register which hold data passing from the processor to the memory

Data in registers which hold data passing from the memory to the processor

instruction decode and control decodes machine instruction into control signals for the datapath

Addrress Bus Address bus is a one-way path from processor to memory which specifies the location of the memory element being accessed

Data Bus Data bus is a two-way path between processor and memory which transfers data

Store data from Rd to memory address
STR Rd, [Rn, Offset]

Instruction
Decode
Control

This tour demonstrates the functionality of this tool

This diagram shows the organisation of the ARM processor. It is the 3-stage pipeline ARM organisation

These boxes provide explanation about the execution of the instruction in the ARM processor

The run button starts the instruction execution. After you press run, a stop button will appear to halt the execution

The step button goes through the instruction execution step by step

The previous button goes back to the preceding step

The invisible button removes the background diagram of the processor and displays only the parts of the processor in use. After you press invisible, a visible button will appear to display the diagram again

The invisible button removes the background diagram of the processor and displays only the parts of the processor in use. After you press invisible, a visible button will appear to display the diagram again

Press on the highlighted units to get further information about these components

Store data from Rd to memory address STR Rd, [Rn, Offset]

Instruction Decode Control

This tour demonstrates the functionality of this tool

This diagram shows the organisation of the ARM processor. It is the 3-stage pipeline ARM organisation

These boxes provide explanation about the execution of the instruction in the ARM processor

The run button starts the instruction execution. After you press run, a stop button will appear to halt the execution

The step button goes through the instruction execution step by step

The previous button goes back to the preceding step

The invisible button removes the background diagram of the processor and displays only the parts of the processor in use. After you press invisible, a visible button will appear to display the diagram again

The invisible button removes the background diagram of the processor and displays only the parts of the processor in use. After you press invisible, a visible button will appear to display the diagram again

Press on the highlighted units to get further information about these components

Store data from Rd to memory address
STR Rd, [Rn, Offset]

Instruction
Decode
Control